Device Tree Architect | Xilinx Ethernet Configuration

⚠️ Work in Progress

This tool is under active development and may not provide 100% accurate device trees for all boards. Pending verification across all supported configurations. Use with caution and always verify generated device trees against your hardware documentation.

Board Configuration

Select Board

Vivado Version

Design Template

PS Ethernet (Processing System)

Select a board and version first

PL Ethernet (Programmable Logic)

Select a board and version first

Block Diagram

MIO Multiplexed I/O

EMIO Extended MIO

GTR Gigabit Transceiver

Device Tree Source

Select a board and configure ethernet nodes to generate DTS