🔌 ZCU102 Ethernet Interface Architecture Map

Interactive Guide to PS-GEM Device Tree Configurations

📦 Version Coverage: 2019.1 → 2024.2

🏗️ Complete System Architecture

graph TB A[ZynqMP PS
Processing System] --> B{GEM Controller
Gigabit Ethernet MAC} B -->|MIO Path| C[RGMII Interface
Reduced GMII] B -->|EMIO Path| D[PL Logic
Programmable Logic] B -->|GTR Path| E[PS-GTR Serdes
Transceiver] C --> F[ EXT PHY
For eg. TI DP83867 PHY
Physical Layer IC] F --> G[RJ45 Port
1000BASE-T] D --> H[PCS/PMA IP
1G/2.5G Subsystem] H --> I[SFP+ Cage
1000BASE-X/SGMII] E --> J[SFP+ Cage or EXT PHY
Direct Serdes] style A fill:#667eea,stroke:#764ba2,stroke-width:3px,color:#fff style B fill:#764ba2,stroke:#667eea,stroke-width:3px,color:#fff style F fill:#51cf66,stroke:#40c057,stroke-width:2px,color:#fff style H fill:#f093fb,stroke:#f5576c,stroke-width:2px,color:#fff style E fill:#4dabf7,stroke:#339af0,stroke-width:2px,color:#fff style G fill:#69db7c,stroke:#51cf66,stroke-width:2px style I fill:#faa2c1,stroke:#f093fb,stroke-width:2px style J fill:#74c0fc,stroke:#4dabf7,stroke-width:2px

📘 About This Guide

This comprehensive reference documents all PS-GEM (Processing System Gigabit Ethernet MAC) device tree configurations for the ZCU102 evaluation board across multiple Vivado/PetaLinux versions. Use the interactive sections below to explore each pathway, view actual device tree nodes, and understand the complete signal chain from software to hardware.

🟢 MIO Pathway

PS-GEM → MIO → RGMII → TI PHY → RJ45

Technical Specifications

  • Interface: RGMII (Reduced Gigabit Media Independent Interface)
  • PHY Type: TI DP83867 (10/100/1000BASE-T)
  • PHY Address: 0x0C (MDIO bus)
  • Speed Support: 10/100/1000 Mbps auto-negotiation
  • Connector: RJ45 on-board jack
  • Use Case: Standard Ethernet, easiest to configure

🔴 EMIO Pathway

PS-GEM → EMIO → PCS/PMA → SFP+

Technical Specifications

  • Interface: GMII via EMIO (Extensible MIO)
  • PL IP: 1G/2.5G Ethernet PCS/PMA or SGMII
  • PHY Mode: 1000BASE-X or SGMII
  • PHY Address: Typically 0x09 (internal to PL IP)
  • Connector: SFP cage (fiber or copper SFP)
  • Use Case: Flexible, programmable logic integration

🔵 PS-GTR Pathway

PS-GEM → PS-GTR → SFP+

Technical Specifications

  • Interface: Native PS-GTR transceiver
  • Protocol: 1000BASE-X or SGMII over GTR
  • Lane Assignment: GTR Lane 0/1/2/3 (configurable)
  • Speed Support: 1.25 Gbps line rate
  • Connector: Direct SFP+ connection
  • Use Case: High-performance, low-latency path

📄 Device Tree Node Examples

Real device tree snippets from ZCU102 reference designs (2024.2). Scroll below to browse all versions and designs with complete device trees. Need to create your own? Try our Device Tree Architect ⚙️ tool!

⚠️ IMPORTANT: Final Device Tree Source

The device tree code shown on this page represents the FINAL compiled output from the system.dtb file. These nodes are the result of PetaLinux build process which combines base device trees with custom overrides from system-user.dtsi. To understand the full device tree override required for each design, please visit the ZCU102-Ethernet GitHub repository directly!

⚙️ Need to Create Custom Device Trees?

Use Device Tree Architect - an interactive tool that helps you generate custom Ethernet device tree configurations with board-aware smart suggestions and real-time validation.

Launch Device Tree Architect →
📁 2024.2/ps_mio_eth_1g - PS GEM3 (MIO) with RGMII 
ethernet@ff0e0000 {
    compatible = "xlnx,zynqmp-gem", "cdns,gem";
    status = "okay";
    phy-handle = <&phy0>;
    phy-mode = "rgmii-id";
    
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: ethernet-phy@c {
            reg = <0xc>;
            ti,rx-internal-delay = <0x8>;
            ti,tx-internal-delay = <0xa>;
            ti,fifo-depth = <0x1>;
            ti,dp83867-rxctrl-strap-quirk;
        };
    };
};
📁 2024.2/ps_emio_eth_1g - PS GEM0 (EMIO) with GMII with PL PCS/PMA IP 
ethernet@ff0b0000 {
    compatible = "xlnx,zynqmp-gem", "cdns,gem";
    status = "okay";
    phy-handle = <&phy0>;
    phy-mode = "gmii";
    
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: ethernet-phy@9 {
            reg = <0x9>;
            xlnx,phy-type = <0x5>;
        };
    };
};
📁 2024.2/ps_emio_eth_sgmii - PS GEM0 (EMIO) with GMII with PL PCS/PMA IP 
ethernet@ff0b0000 {
    compatible = "xlnx,zynqmp-gem", "cdns,gem";
    status = "okay";
    phy-handle = <&phy0>;
    phy-mode = "gmii";
    
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: ethernet-phy@9 {
            reg = <0x9>;
            xlnx,phy-type = <0x4>;
        };
    };
};
📁 2024.2/pl_eth_1g - PL Ethernet with 1000Base-X 
ethernet@a0000000 {
    compatible = "xlnx,axi-ethernet-7.2", "xlnx,axi-ethernet-1.00.a";
    device_type = "network";
    reg = <0x0 0xa0000000 0x0 0x40000>;
    interrupts = <0x0 0x59 0x4 0x0 0x5a 0x4>;
    phy-mode = "1000base-x";
    xlnx,rxmem = <0x1000>;
    xlnx,txcsum = <0x0>;
    xlnx,rxcsum = <0x0>;
    phy-handle = <&phy1>;
    
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy1: ethernet-phy@1 {
            device_type = "ethernet-phy";
            reg = <0x1>;
            xlnx,phy-type = <0x5>;
        };
    };
};
📁 2024.2/pl_eth_sgmii - PL Ethernet with SGMII 
ethernet@a0000000 {
    compatible = "xlnx,axi-ethernet-7.2", "xlnx,axi-ethernet-1.00.a";
    device_type = "network";
    reg = <0x0 0xa0000000 0x0 0x40000>;
    interrupts = <0x0 0x59 0x4 0x0 0x5a 0x4>;
    phy-mode = "sgmii";
    xlnx,rxmem = <0x1000>;
    xlnx,txcsum = <0x2>;
    xlnx,rxcsum = <0x2>;
    phy-handle = <&phy2>;
    
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy2: ethernet-phy@1 {
            device_type = "ethernet-phy";
            reg = <0x1>;
            xlnx,phy-type = <0x4>;
        };
    };
};
📁 2024.2/pl_eth_10g - PL 10G/25G Ethernet with 10GBase-R 
ethernet@a0040000 {
    compatible = "xlnx,xxv-ethernet-4.1", "xlnx,xxv-ethernet-1.0";
    device_type = "network";
    reg = <0x0 0xa0040000 0x0 0x40000>;
    interrupts = <0x0 0x59 0x4 0x0 0x5a 0x4>;
    phy-mode = "10gbase-r";
    xlnx,rxmem = <0x1000>;
    xlnx,channel-ids = <0x1>;
    local-mac-address = [00 0a 35 00 22 01];
    phy-handle = <&phy3>;
    
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy3: ethernet-phy@4 {
            device_type = "ethernet-phy";
            reg = <0x4>;
            xlnx,phy-type = <0x5>;
        };
    };
};

📊 Device Tree Data Availability Matrix

Device tree data availability for each design across Vivado/PetaLinux versions. ✓ = Available, ✗ = Not Available

Design Type 2020.1 2020.2 2021.1 2021.2 2022.1 2022.2 2023.1 2023.2 2024.1 2024.2
ps_mio_eth_1g ✓ ✓ ✓ ✗ ✓ ✓ ✓ ✓ ✓ ✓
ps_emio_eth_1g ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
ps_emio_eth_sgmii ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
pl_eth_1g ✓ ✓ ✓ ✗ ✓ ✓ ✓ ✓ ✓ ✓
pl_eth_sgmii ✓ ✓ ✓ ✗ ✓ ✓ ✓ ✓ ✓ ✓
pl_eth_10g ✓ ✓ ✓ ✗ ✓ ✓ ✓ ✓ ✓ ✓

📌 Note on Device Tree Availability

All six design types are available in the ZCU102-Ethernet repository for all versions shown. This matrix indicates which device tree data has been successfully parsed and is available for browsing below. Missing entries (✗) may be due to incomplete parsing, missing DTS files, or configurations not yet extracted.

📦 Source Repository: ZCU102-Ethernet on GitHub

🔍 Browse All Device Tree(s)

Filter and search through all extracted device tree ethernet configurations. Only showing active/enabled ethernet interfaces in each design!

📦 Download All Device Trees

Download a complete archive of all extracted device tree source files for offline reference.

📥 Download extracted_dts.zip

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📚 ZCU102 Ethernet Interface Architecture Map

January 2026

Displaying parsed device tree data from 57 design configurations